Xiaofeng Gao

aka Gaofeng or Feng Gao
Ph. D Student in CSE Dept. UCSD

9500 Gilman Dr #0114, La Jolla, CA, 92037

Publications
C.V.
I passed my defense on March 10th, 2006. Here is my thesis and my defense slides.

I am a fifth year graduate student in PMaC lab.
My advisors are Professor Larry Carter and Professor Allan Snavely

My research interests include

Binary instrumentation
Methods to reduce overheads of profiling and tracing
Trace representation, characterization, compression and processing
Code generation and scheduling
Performance modeling, tuning and prediction

I like to work with low level instruction sequences. I am experienced the ISAs of IBM Power family processors, Intel IA32/IA64 processors, Alpha processors. I have created several tools to analyze binary codes for constant static behaviors so we can reduce the overheads of dynamic tracing and profiling.

I have authored PowerSIM, a simulator specially desinged for IBM Power 4 processors. This simulator incorporates various hardware features of the processor and has been shown to generates very close performance data compared to HPM counters. This simulator is based on SimpleScalar but it is focused on FP and MEM units and their interactions. This simulator was used for generating performance surface families

I am experienced with various instrumentation tools. I have ported MetaSim to Alpha using ATOM, IBM POWER using DyninstAPI and Intel IA64 using PIN . I also got a chance to use Vulcan, BBT and Nirvana from Microsoft and VTune from Intel while I was doing intern at Microsoft Research during the summers of 2003 and 2004. I also created ALiTER, which is extremely lightweight for fine-grained instrumentation compared to generic tools such as ATOM, PIN and Dyninst

Last Update 21 Sept. 2005