Hongyu Chen        Ph.D. Candidate  Department of Computer Science and Engineering  University of California, San Diego  Email: hchen@cs.ucsd.edu    Full List of Publications   C.V.   Research Statement   Teaching Statement

My research interests include

• Algorithms for Computer Aided Design of Very Large Scale Intergrated Circuits (VLSI CAD)
• On-Chip Interconnect Architectures
• Clock and Power Distributions
• Network-On-Chip
• Network Flow and other combinatorial Optimizations

  Selected Publications:

• H. Chen, C. K. Cheng, A. B. Kahng, I. Mandoiu, Q. Wang, and B. Yao, "The Y-Architecture for On-Chip Interconnect: Evaluations and Methodologies," IEEE Transactions on Computer Aided Design of Integrated Circuites and Systems, to appear May 2005
   
• H. Chen, M. Mori, B. Yao, and C. K. Cheng, "A Multi-Level Network Approach for Clock Skew Minimization Under Process Variations," submitted to IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. (Preliminary version published on Asia and South Pacific Design Automation Conference, 2004)
   
• H. Chen, and C. K. Cheng, "A Multi-Level Transmission Line Network Approach for Multi-Giga Hertz Clock Distribution," Asia and South Pacific Design Automation Conference, 2005
   
• B. Yao, H. Chen, C. K. Cheng, and R. Graham, "Floorplan Representations: Complexities and Connections," ACM Transactions on Design Automation of Electronic Systems, vol.8(1), pp.55-80, February 2003
   
• H. Chen, B. Yao, F. Zhou, and C. K. Cheng, "Physical Planning of On-Chip Interconnect Architectures," IEEE International Conference on Computer Design, 2002