CSE 141 Ungraded Homework # 3

Recommended "due date" - Feb 8.

  1. Print out slides 20 and 21 in the lecture for Feb 6 (titled The Store Datapath and The beq Datapath) highlight the datapath and (as was done on slides 18 and 19), and figure out how the control signals need to be set.
  2. Assume that both memory units take 1 nanosecond for a read, the ALU and adders take 0.5 ns, the register file takes 0.4 ns, and multiplexors take 0.1 ns. Also assume the sum of the state elements' setup and hold times is 0.2 ns. Determine how long each of the four types of instructions would take in the single-cycle design. What clock speed (in MHz) can this design run at?
  3. Problem 5.1 on page 427 of the textbook.