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Core-based SOC test:
The overall cost of testing a core in a System-On-a-Chip (SOC) consists of
the generation of a test for the core and application of this test to the
core. Test generation for the core necessitates the utilization of
structural information about the core that is available at the core vendor
side; the test set generated is provided to the system integrator along
with the core. It is the system integrator's responsibility to implement
the on-chip Test Access Mechanism (TAM) that helps transport the test data
between the I/Os of the core and the chip. Core test scheduling is
performed by the system integrator to efficiently distribute the tester
bandwidth to cores and hence minimize the test costs such as test
application time and volume with no test power violations.
Test cost can be reduced at the core vendor side through efficient
high-level test generation and fault simulation techniques rather than
costly gate-level approaches. Design hierarchy along with module
functionality can be exploited to benefit from the rapid propagation
through the high-level modules. Even though abstraction at higher levels
helps hide the complexity of the gate-level approaches, utilization of
fault models defined at higher levels results in a loss of accuracy. Being
able to report gate-level fault coverages and yet achieving significant
speed-ups necessitates the implementation of high-level
methodologies efficiently coupled with gate-level schemes.
To reduce the required test bandwidth associated with the test access
mechanism and hence to enable parallel testing of cores, output compaction
and test data compression techniques can be employed. While the bandwidth
is narrowed down in both techniques, keeping the original fault coverage
intact becomes challenging; the actual set of test vectors should be
constructed out of the compressed test data and all the originally
detectable faults should still be detected at the compactor's outputs.
Furthermore, even though the consequent parallelism among core tests helps
reduce the test application time, the increase in test power dissipated
endangers the reliable testing of the chip. The unnecessary transitions
that occur in the scan chain during the shift of the test data reflect
into the cores, creating rippling inside the cores being tested. To enable
both reliable and cost-effective testing of SOC designs, the techniques
that reduce the required test bandwidth should be complemented with efficient test power management schemes.
Test Power Dissipation:
In a scan-based environment, wherein the original flip-flops of the
circuit are all converted into fully accessible scan cells, shift
operations activate all the scan cells in the circuit at any instance.
Such a scenario is never encountered in normal operation of the chip, as
typically the majority of the flip-flops are idle. In current designs, the
circuits are controlled mostly by the flip-flops rather than the primary
inputs; changes in flip-flop values strongly determine the power
dissipation. Consequently, during the shift operations in test mode, the
power dissipation significantly exceeds the power dissipation of the
normal mode. The major contributor of the power dissipation during test
mode is the switching activity that occurs inside the circuit; the
switching activity stems from the transitions in the scan cells. The
excessive power dissipation during shift cycles may endanger the
reliability of the chip being tested, as exceeding certain power
thresholds may damage the chip. Furthermore, due to overheating, the chip may yield
responses that differ from the expected responses, resulting in the
incorrect classification of functional chips as defective.
Our research in this area aims at reducing scan chain transitions, thus
cutting down power dissipation. The power dissipation is determined by the
stimulus inserted into the scan chain and the response observed through
the scan-out pin. In traditional test, the stimulus inserted into the scan
chain is identical as the test vector to be applied to the circuit;
similarly, the response captured in the scan cells and the response
shifted out are identical. We have proposed a number of techniques that
break this equivalence by inserting logic gates between the scan cells.
The consequent test data transformations enable the shifting in (out) of
power-wise efficient stimuli (responses); the transformations are confined
to bijective ones, ensuring the delivery of the actual test vectors and
the observation of any captured fault effects. The actual fault coverage
is preserved, consequently. Furthermore, the logic gates are inserted on
the test path, with no introduction of gate delay!
s on critical paths of the circuit, resulting in no impact on the
functional operation of the chip timing-wise.
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