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Continuous improvements in silicon manufacturing technology have enabled
the realization of extremely large and complex designs that have by far
outpaced the capacity of the EDA tools to handle them as monolithic
entities. Hierarchical approaches help reduce the computational complexity
associated with test-related processes; local tests can be quickly and
efficiently generated for each module of a hierarchical design and
consequently translated to global test, applicable at the complete design
boundary.
The success of the hierarchical approaches strongly relies on the efficacy
of the test translation process. Exhaustive search techniques applied on
the functional space of the upstream vector justification and downstream
response propagation logic are doomed by complexity. Our research in this
area has focused on the identification of bijective reachability paths
from the circuit I/Os to the module I/Os, enabling the translation of any
local vector into a system-level test. The reachability analysis not only
helps construct the reachability paths but furthermore the hierarchical
constraints for the module under analysis are identified as well. These
constraints can also be incorporated into the local test generation
process, resulting in the generation of local tests that can be translated
into system-level tests.
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