UCSD RSSL
Computer Science and Engineering


ALEX
ORAILOGLU


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RSSL
- CSE140 - Components and Design Techniques for Digital Systems:
- [Winter 04] [Spring 03] [Winter 03] [Winter 02]
- Units: 4
- Description: This course gives an introduction to digital logic design. The Lab course CSE 140L covers software and hardware projects: Design of Boolean logic and finite state machines; two-level, multi-level combinational logic design, combinational modules and modular networks, Mealy and Moore machines, analysis and synthesis of canonical forms, sequential modules.

- CSE140L - Digital Systems Laboratory:
- [Winter 04] [Spring 03] [Winter 03] [Winter 02]
- Units: 2
- Description: This Lab course covers software and hardware projects. The course runs concurrently with CSE 140: Implementation with computer-aided design tools for combinational logic minimization and state machine synthesis. Hardware construction of a small digital system.

- CSE144 - Computer-Aided Design of VLSI Circuits:
- [Fall 01] [Spring 99] [Spring 98]
- Units: 4
- Description: This course provides a survey of advanced techniques for solving computer-aided design problems for a wide range of design styles. A technology-independent description is followed to provide algorithms and techniques that are applicable for a wide range of fabrication processes. The course is a departure point for research in Computer-Aided Design: Introduction to Computer-Aided Design. Placement, Assignment and Floor Planning Techniques. Routing. Symbolic Layout and Compaction. Module generation and silicon compilation.

- CSE240A - Principles in Computer Architecture:
- [Winter 04] [Fall 01] [Spring 01]
- Units: 4
- Description: This course will cover fundamental concepts in computer architecture. Topics include instruction set architecture, pipelining, pipeline hazards, bypassing, dynamic scheduling, branch prediction, superscalar issue, memory-hierarchy design, advanced cache architectures, and multiprocessor architecture issues.

- CSE243A - Introduction to Synthesis Methodologies in VLSI CAD:
- [Winter 03] [Winter 02] [Spring 01]
- Units: 4
- Description: Hardware software co-design, architectural level synthesis, control synthesis and optimization, scheduling, binding, register and bus sharing, interconnect design, module selection, combinational logic optimization, state minimization, state encoding, and retiming.


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Last modified Sunday, October 26, 2003 at 15:31:00