This group is advancing the state-of-the-art in processor architecture and compilers, examining techniques that both expose higher levels of instruction-level parallelism (ILP) to the processor and allow the processor to exploit more of that parallelism. The current focus is on new architectural techniques and compiler optimizations aimed at high-performance processors and compiling for current and future high-ILP processors. Active areas of research include Simultaneous Multithreading (SMT) and compiler optimizations for ILP.

SMT is an architecture that allows the processor to exploit ILP between separate threads (programs) running on the processor, even within a single cycle, with minimal changes to current superscalar designs. SMT raises new architectural issues and challenges many traditional assumptions about processor architecture and compilation. Proposed extensions to our SMT architecture can nearly eliminate the branch prediction penalty, even without multiple threads running. This is done by using idle processor resources to follow multiple paths through a traditional, single-threaded application.

The interaction between compilers and computer architecture is an important part of performance for future processors. This interaction is the basis for much of our compiler research. The topics being investigated include improving memory system performance through code and data layout compiler transformations, predicated execution, compiling for SMT, statically and dynamically estimating future behavior of an application, profiler-based optimizations, link-time and run-time optimizations, just-in-time compiling, and dynamic compilation.