Helpful information for Xilinx

• Xilinx Webpack Tutorial - VHDL + ModelSim Simulation

• A tutorial on using BUS in Xilinx ISE

• A tutorial on creating simple finite state machine using VHDL

• A sample Xilinx generated timing diagram.

• Here is the tutorial on how to build RAMs and ROMs in Xilinx. You can cut and paste to avoid typos. Clearly all the "data" that you store in your RAMs and ROMs will be VERY different and MUCH longer. This is a sample. You also only need to make your memory as big as you need it -- in terms of number of bits to address.