Some answers

1. False. (DRAM capacity, not speed, is improving dramatically.)
2. True.
3. False. (Cache is typically SRAM.)
4. True.
5. True.
6. Spatial Locality.
7. Greater flexibility. (Credit also given for "Faster speed".)
8. Various possible answers.
9. Ditto.
10. The answer I wanted was, "Pipelining improves Seconds/Cycle" but "CPI" was also considered correct. Parallelism improves CPI.
11. The article thinks that a millisecond is a millionth of a second, but it's really a thousandth. This makes RAM 150,000 times as fast, which strengthens the point being made.
12. (a) 25 MIPS.
    (b) 2.5 cycles/instruction.
    (c) 1.28 times faster. (credit also given for .28 times faster ... the question should have said "___ times as fast.")
    (d) 28%.
13. (a)Formulas
    Time to reload cache (sec) = number of cachelines x time to reload one line (sec)
    Time to reload one line (sec) = cache miss penalty (cycles) / clock speed (cycles/sec)
    Number of cachelines = cachesize (Bytes) / blocksize (Bytes)
    Estimates and calculations
    Various answers are possible. (A blocksize of 4 KByte is not reasonable, particularly for a 32 KByte cache.)
    (b)Ten or 11 times the answer to part (a) were acceptable answers.
14. (a) The 4th and 7th memory references were hits.
    (b)

    Index	Valid	Tag
    00	1	010
    01	0	N/A
    10	1	000
    11	1	011

15. (a) The first 11 bits (from the left) should be circled.
    (b) The 6-th to 11-th bits (from the left) should be circled.
    (c) The first to fifth (from the left) should be circled.