General note: Stalls due to data hazzards prevent the ID stage from completing. If one instruction hasn't completed the ID stage, the next can't complete its IF stage. 2(a) No forwarding, hardware assumes (correctly) branch not taken. sll $2, $2, 2 IF ID EX MEM WB sub $5, $5, $5 IF ID EX MEM WB lw $8, 1000($2) IF - - ID EX MEM WB add $5, $5, $8 IF - - - ID EX MEM WB addi $2, $2, -4 IF ID EX MEM WB bne $2, $0, loop IF - - - ID EX MEM WB sw $5, 500($0) IF ID EX MEM WB 2(b) No forwarding, hardware assumes branch not taken but branch is taken. bne $2, $0, loop IF ID EX MEM WB (see note 1) sw $5, 500($0) IF ID EX (see note 2) lw $8, 1000($2) IF ID EX MEM WB add $5, $5, $8 IF - - - ID EX MEM WB addi $2, $2, -4 IF ID EX MEM WB bne $2, $0, loop IF - - - ID EX MEM WB Note 1: A more accurate diagram has 3 stall cycles in the first bne, waiting for the data from register $2 from the previous addi instruction. Note 2: The sw and probably several other instructions begin execution before the branch is determined to be taken. But they are killed before they write anything into registers or memory. 2(c) Switching the positions of the add and addi instructions would eliminate stall cycles. The loop body of the new code would appear as shown below and contain 2 stalls per iteration (in addition to the cycles lost on the branch). bne $2, $0, loop IF ID EX MEM WB sw $5, 500($0) IF ID EX lw $8, 1000($2) IF ID EX MEM WB addi $2, $2, -4 IF ID EX MEM WB add $5, $5, $8 IF - - ID EX MEM WB bne $2, $0, loop IF ID EX MEM WB 2(d) with forwarding sll $2, $2, 2 IF ID EX MEM WB sub $5, $5, $5 IF ID EX MEM WB lw $8, 1000($2) IF ID EX MEM WB add $5, $5, $8 IF - ID EX MEM WB addi $2, $2, -4 IF ID EX MEM WB bne $2, $0, loop IF ID EX MEM WB sw $5, 500($0) IF ID EX MEM WB