Homework #3 Solutions

  1. Machine code: 10101100010001000000000000001000
    Mem[36-39] = 44

  2. Machine code: 00000000000000010001000000100000
    r2 = 8

  3. Machine code: 00100000101001101111111111111100
    r6 = 32

  4. The instruction is (1+1+2) = 4 bytes long
    Mem[16-19] = 17, r3 = 20

  5. Stack architecture
    push b Code Size Data Size
    push b 3 4
    push c 3 4
    add 1
    pop a 3 4
    push a 3 4
    push c 3 4
    add 1
    pop b 3 4
    push b 3 4
    push c 3 4
    sub 1
    pop d 3 4

    Code size: 30 bytes, Data references: 36 bytes

    Load store architecture
    push b Code Size Data Size
    ld r1,b 4 4
    ld r2,c 4 4
    add r3,r2,1 3
    st a,r3 4 4
    add r4,r1,r3 3
    st b,r4 4 4
    sub r5,r4,r2 3
    st d,r5 4 4
    Code Size: 29 bytes, Data references: 20 bytes

    Load/Store architecture is more efficient in both code size and bandwith.

  6. Convert Sign-Extn block into Sign/Zero-Extn. and add a new contol signal called Unsinged.

    Control signals for Addui:
    RegDest = 1, ALUSrc = 1, Branch = 0, AluOp1 = 0, AluOp2 = 0 MemWrite = 0, MemRead = 0, RegWrite = 1, Unsigned = 1, MemtoReg = 0

    For all others Unsigned = 0.