CSE 141 Homework # 3

Due May 22. Please see class homepage concerning late assignments and academic dishonesty policies.

For the first four questions, assume that the contents of registers and memory is as indicated below. You should tell all the changes to registers and memory caused by the given instruction. For instance, an answer might be, "After the instruction is executed, register 6 will contain 25, and memory locations 44 to 47 contain 20." (The first three questions should be very easy ... I just want to make sure everyone understands how machine instructions work.)

Treat each question separtately, that is, the memory and registers always start as shown below.

Registers (This shows the contents of the first 8 registers. The values are expressed in decimal.)

0
Reg 0 		8
Reg 1 		28
Reg 2 		16
Reg 3		 44
Reg 4		 36
Reg 5		 20
Reg 6		 20
Reg 7

Memory (This shows the contents of the first 64 Bytes of main memory, where each 4-Byte word is shown as a decimal number.)

20
Bytes 0 to 3		 16
 4 to 7		 12
 8 to 11		 8
 12 to 15		 4
16 to 19		 0
20 to 23		 24
24 to 27		 32
28 to 31
3148
Bytes 32 to 35		 24
36 to 39		 0
40 to 43		 4
44 to 47		 44
48 to 51		 17
52 to 55		 16
56 to 59		 12
60 to 63

  1. For the MIPS assembly instruction sw $4,8($2),
    (a) Write the machine instruction in binary (yes, I want you to write out 32 0's and 1's.) The charts inside the back cover of the textbook should help. Please note that the order of the operands in assembly code is different from the order in machine code.
    (b) Tell how registers and/or memory would be changed.

  2. For the MIPS instruction add $2,$0,$1,
    (a) Write the instruction in binary, and
    (b) Tell how registers and/or memory would be changed.

  3. For the MIPS instruction addi $6,$5,-4,
    (a) Write the instruction in binary, and
    (b) Tell how registers and/or memory would be changed.

  4. For the VAX 11 instruction, movl (r3)+ (r6)[r1],
    (a) Figure out how many bytes the instruction takes (note: in figure E2 where the book says in, "1 + length of base addressing mode", it should say, "2"). Incidentally, the "l" in movl is the letter "L" and means the operands are 4-Byte numbers.
    (b) Tell how registers and/or memory would be changed.

  5. Problem 3.26, but only for the Stack and Load-Store architectures.

  6. Problems 5.11 and 5.12 in the text. Despite what the book says, I don't think addiu is described in Chapter 3. For the purpose of this problem (even though it may not be true), assume that addiu is like addi, except that it doesn't extend the sign of the immediate operand. (Also, addiu can't cause an interrupt, but you needn't be concerned with that.)