CSE 141 Homework # 2

The human brain has about ten billion (10^10) neurons. Each neuron has about 100,000 (that is, 10^5) connections to other neurons. Each neuron can fire about 1000 times a second.

(a) Estimate (using the BotEC format) how powerful the human brain is compared to a modern microprocessor chip (such as the Intel Pentium Pro or IBM PowerPC). To do so, assume that, at each timestep, the "computation" represented by whether a neuron will fire or not corresponds to the amount of computation done by about 100,000 transistors (one per neural connection) executing for one clock cycle.

(b) Assume that the number of transistors on a processor chip will increase at the same rate that DRAM has improved, and that the clock speed of microprocessors will continue to improve at the same rate that microprocessor clock speeds have improved in the last 5 or so years (note: this is faster than the improvement in DRAM speeds!) Make a BotEC calculation of how much single-chip microprocessors are improving per year, when microprocessor performance is measured by "transistor-cycles per second". (Note: Your answer should be a unitless number, representing the factor that you should multiply one year's performance by to get the next year's performance. Since I'm asking that you consider "transistor-cycles per second" as the performance measure, your answer will probably be different than the improvement in microprocessor power when measured by the traditional measures like MIPS or MFLOPS).

(c) Using your estimates, calculate in what year a single-chip microprocessor will have more computational power than a human's brain. (Actually, human brains are improving too, due to evolution, nutrition, and possibly education, but you may ignore this in your calculation.) Hint: since we're assuming that the power of a chip is increasing by a constant multiplicative factor each year, the logarithm of the chip's power is increasing by an additive constant per year.

A certain database searching benchmark program makes 27,000 disk read operations, each for a block of 1024 Bytes of data. An enterprising young engineer realized that if the program would use larger blocks, then the number of read operations would be reduced. She performed extensive tests, and discovered that for every doubling of the block size, the number of read operations is reduced to 2/3's of its value. (For instance, for a block length of 2048 bytes, there are 27,000 x 2/3 = 18,000 read's.)

Suppose that all disk reads have an average latency of 10 milliseconds until the requested block is found on disk, and then the data is transferred to memory at a rate of 2 MByte/sec.

For the purpose of this problem, we assume that the disk access can't be pipelined. Thus, for example, the 10 millisecond latency of the second read CANNOT overlap the transfer time of the first read.

Make a table (similar to the one shown) that, for block sizes that are a power of two, from 2^10 Bytes to 2^18 Bytes, shows (a) the average wallclock time to perform a read operation (don't forget to add in the 10 millisecond latency), (b) the number of disk reads required by the benchmark, (c) the total amount of data that is brought in from disk during the benchmark, and (d) the total time spent doing reads from disk for the benchmark.

Also answer these questions:

• Which block size gives the best performance? (NOTE: I've constructed this problem so that the answer is neither the largest nor the smallest block size. If your answer is one of these extreme values, either you or I have made a mistake.)
• Would the best block size be different if the benchmark required more disk read operations? If so, would it be larger, smaller, or depend on how many more disk reads there were? (Note: the best way to answer this and the next question is to try to develop some intuition about what's going on.)
• Would the best block size be different if the disk latency were reduced? If so, would it be larger, smaller, or depend?

Do problems 7.1, 7.2, and 7.3 in the textbook (page 527).