Date: Nov 4, 1998

When: 4pm-5:30pm

Where: AP&M 4301

Title: Processor Architecture and Compilation Lab

Speakers: Brad Calder and Dean Tullsen

Abstract:

The Processor Architecture and Compilation Lab (PACL) conducts
research into computer architecture and compiler optimizations.

Brad Calder will be talking about a mixture of research areas
including value prediction, compiler optimizations for improved memory
performance, and faster mobile computing.  Value prediction is the
process of breaking true data dependencies during execution in a
program by predicting the result value for an instruction before the
real result is available.  This is a new speculation technique, which
can potentially provide large performance gains by reducing the
lengths of the critical paths through a program.  The compiler
research focuses on rearranging code and data to eliminate cache
conflicts.  In addition, we have examined using these code placement
techniques to provide faster execution for mobile Java programs.


Dean Tullsen will also address a mixture of research topics.  He
will introduce simultaneous multithreading (SMT), a technique that allows
a processor to issue and execute instructions from multiple threads
(execution streams) in the same cycle.  It allows a conventional
processor to get substantially higher throughput with relatively small
changes to the execution core.  He will describe the current state
of the SMT research, including hardware-generation of threads,
compiler techniques, synchronization optimizations, and low-power
optimizations.  He will also describe some new directions in
critical-path computing.