RASIT ONUR TOPALOGLU, Ph.D. E-mail: username: rtopalog hostname: cs.ucsd.edu Phone: (858) 366-2301 Address: 9500 Gilman Drive CSE Departmant La Jolla, CA 92093

Former Research Assistant in Reliable System Synthesis Lab
Former Research Assistant in VLSI CAD Lab
Worked part time at National Semiconductor (2004), Qualcomm (2003 and 2005) and AMD (2005)
Full time employee (Technology and Integration Engineer) at Advanced Micro Devices since 2006  

Research Interests:

Computer-Aided Design (Design for Manufacturability, TCAD, RC Extraction)
Process, Device, Interconnect and Circuit Modeling
Design and Design for Test (RF, analog, digital)

Publications

2008 [J6] Andrew B. Kahng, P. Sharma and R.O. Topaloglu, "Chip optimization through STI stress-aware placement perturbations and fill insertion," accepted for publication in IEEE Trans. on Computer-Aided Design, 2008. [C17] R.O. Topaloglu, "Process variation characterization and modeling of nanoparticle interconnects for foldable electronics," Proc. IEEE International Symposium on Quality Electronic Design, 2008. [J5] A.B. Kahng and R.O. Topaloglu, "DOE-based extraction of CMP, active and via fill impact on capacitances," IEEE Trans. on Semiconductor Manufacturing, 21(1), 2008, pp. 22-32.

2007 [C16] R.O. Topaloglu, "Via chamfering modeling for improved MIM capacitance silicon correlation," Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007. [C15] A.B. Kahng and R.O. Topaloglu, "Performance-aware CMP fill pattern optimization," Invited Paper, Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007. [C14] A.B. Kahng, P. Sharma and R.O. Topaloglu, "Exploiting STI stress for performance," Proc. IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 83-90. [C13] R.O. Topaloglu, "Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization," Proc. IEEE Custom Integrated Circuits Conference, 2007, pp. 619-622. [C12] A.B. Kahng and R.O. Topaloglu, "A DOE set for normalization-based extraction of fill impact on capacitances," Best Paper Award, Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 467-474. [C11] R.O. Topaloglu, "Energy-minimization model for fill synthesis," Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 444-451. [C10] A.B. Kahng and R.O. Topaloglu, "A TCAD-based study of fill pattern and via fill impact on low-k dielectric stress," Invited Paper, Proc. International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC), 2007, pp. 337-346. [J4] R.O. Topaloglu, "Process variation-aware multiple-fault diagnosis of thermometer-coded current-steering DACs," IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, 54(2), 2007, pp. 191-195.

2006 [C9] A. B. Kahng and R. O. Topaloglu, "Interconnect matching design rule inferring and optimization through correlation extraction," Proc. IEEE International Conference on Computer Design, 2006, pp. 222-229. [C8] R.O. Topaloglu, "Monte Carlo-alternative probabilistic simulations for analog systems," Proc. IEEE International Symposium on Quality Electronic Design, 2006, pp. 249-253. [C7] A.B. Kahng and R.O. Topaloglu, "Generation of design guarantees for interconnect matching", Proc. IEEE/ACM System Level Interconnect Prediction Workshop, 2006, pp. 29-34. [C6] R.O. Topaloglu, "Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations," Proc. IEEE VLSI Test Symposium, 2006, pp. 136-142. [C5] V. Wason, J.X. An, J.-S. Goo, Z.-Y. Wu, Q. Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney, and A. Icel, "Statistical compact modeling and Si verification methodology," Invited Paper, Proc. International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2006, pp. 1198-1201. [J3] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu, H. Kuntman and A. Morgul, ``Novel multiple function analog filter structures and a dual-mode multifunctioni filter ," International Journal of Electronics, 93(9), 2006, pp.637-650, DOI: 10.1080/00207210600711713. Listed as #5 in 2006 most downloaded articles.

2005 [C4] R.O. Topaloglu and A. Orailoglu, "Forward discrete probability propagation method for device performance characterization under process variations," Proc. Asia and South Pacific Design Automation Conference, 2005, pp. 220-223. [C3] R.O. Topaloglu and A. Orailoglu, "A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs," Proc. IEEE/ACM/EDAC Design Automation Conference, 2005, pp. 851-856.

2004 [C2] R.O. Topaloglu, A. Orailoglu, "On mismatch in the deep sub-micron era - from physics to circuits," Proc. Asia and South Pacific Design Automation Conference, 2004, pp. 62-67. [J2] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu and H. Kuntman, "New current-mode special function continuous time active filters employing only OTAs and OPAMPs," International Journal of Electronics, 91(6), 2004, pp. 345-359.

2003 [J1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Current-input current-output notch and bandpass analog filter structures as alternatives to active-R circuits, Frequenz," 57(5-6), 2003, pp. 123-127.

2001 [C1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Novel notch and bandpass filter structures using OTAs and OPAMPs," Proc. International Conference on Electrical and Electronics Engineering, 2001, pp. 63-67.

Patents

5 pending patents, all applied through AMD.

Collaborators

Prof. Andrew Byun Kahng, UCSD
Prof. Alex Orailoglu, UCSD
Puneet Sharma, UCSD
Ali Icel, AMD
Vineet Wason, AMD
Dr. Judy X. An, AMD
Dr. Jung-Suk Goo, AMD
Dr. Z.-Y. Wu, AMD
Dr. Qiang Chen, AMD
Dr. Ciby Thuruthiyil, AMD
Priyanka Chiney, AMD
E. Serkan Erdogan, Duke University
Prof. Oguzhan Cicekoglu, Bogazici University
Prof. Hakan Kuntman, Istanbul Technical University
Prof. Avni Morgul, Bogazici University

Reviewer Duties

IEEE Transactions on VLSI
IET Circuits, Devices and Systems
International Journal of Circuit Theory and Application
Industry liaison for 6 Semiconductor Research Corporation (SRC) projects

Awards

Advanced Micro Devices Author of Merit Award, 2008.
Advanced Micro Devices Technology Development Group Technical Achievement Award, 2008.