Department of Computer Science and Engineering
Mail Code 0114
University of California San Diego
La Jolla, CA 92093 USA
jamison_d_collins@yahoo.com
Personal
I'm a 5th year PhD student in the CSE department at UC San Diego and my advisor
is Dean Tullsen. I
received my Bachelor's degree in Computer Science and Engineering also from UC
San Diego, where I graduated Summa Cum Laude.
Research:
Over the past several decades processor performance has increased at an astonishing rate. This has been driven both by exploiting ever increasing amounts of instruction level parallelism and increasing clock rates. However, as clock frequencies enter the multi-gigahertz range we are face with new challenges. With off-chip memory latencies taking hundreds of cycles to complete, extremely aggressive prefetching techniques are justified and even necessary. Additionally, extremely high clock frequencies limit the maximum size of instruction queues and register files, hindering out ability to extract additional Instruction Level Parallelism from the program (and even causing a reduction in achieved IPC, as in the Pentium IV processor).
My research focuses leveraging the emerging multithreading capabilities of processors (again, such as with the Pentium IV processor and the cancelled 21464) to attack both of these problems. Speculative Precomputation is an aggressive technique for prefetching hard-to-predict load addresses. It does this by extracting the instructions from the main program which are used to compute the load address, and then speculatively executing these instruction sequences (known as Precomputation Slices) in child threads. Because the child threads execute the actual code to produce the future load address, their prefetches are accurate. Precomputation Slices are also significantly shorter than the full program, however, so they execute significantly faster, generating a prefetch in advance of the main program.
As for improving ILP, that is the topic of current research. Stay tuned :).
Research Exam / Thesis Proposal information March 12th 2003 I passed
Pointer-Cache Assisted Prefetching, Jamison Collins, Suleyman Sair, Brad Calder, and Dean Tullsen, In 35th Annual International Symposium on Microarchitecture, November 2002.
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation, Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen, In 8th International Symposium on High-Performance Computer Architecture, February 2002.
Dynamic Speculative Precomputation, Jamison D. Collins, Dean M. Tullsen, Hong Wang, John P. Shen, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).
Speculative Precomputation: Long-range Prefetching of Delinquent Loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen, In 28th International Symposium on Computer Architecture, July, 2001 (see abstract).
Hardware Identification of Cache Conflict Misses, Jamison D. Collins, Dean M. Tullsen, In 32nd Annual International Symposium on Microarchitecture, November, 1999 (see abstract).
Test Publications:
Y. Makris, J. Collins, A. Orailoğlu, "Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface," Journal of Electronic Testing: Theory & Applications, KluwerAcademicPublishers, vol. 18, no. 1, pp. 29-42, 2001
Y. Makris, J. Collins, A. Orailoğlu, P. Vishakantaiah, "Transparency-Based Hierarchical Test Generation for Modular RTL Designs," in Proceedings of the IEEE International Symposium of Circuits and Systems, pp. II 689-692, 2000
Y. Makris, J. Collins, A. Orailoğlu, "How to Avoid Random Walks in Hierarchical Test Path Identification," in Formal Proceedings of the IEEE European Test Workshop, pp. 163-168, 2000
Y. Makris, J. Collins, A. Orailoğlu, "Fast Hierarchical Test Path Construction for Controller-Datapath Circuits without DFT," in Proceedings of the IEEE Asian Test Symposium, pp. 185-190, 2000
Y. Makris, J.
Collins, A. Orailoğlu, "How to Avoid Random Walks in Hierarchical Test
Path Identification," Presented at the
IEEE European Test Workshop, Cascais, Portugal, 2000
Y. Makris, J. Collins, A. Orailoğlu, P. Vishakantaiah, "TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and Hierarchical Test Generation," in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 159-162, 1999